Ankit Gopani

Building and leading Front End DV IP/VIP and methodology teams to address Methodologies and IP/VIP deliverables for 900+ Silicon Engineering department for custom Silicon ASICs programs. Lead successful effort of developing VIPs, evaluating various vendor VIP solutions (AMBA protocols) and migrated these VIP solutions from one vendor to another. Integrating those with IPs, Subsystems and at SoC. Lead team for developing Register models to serve multiple custom silicon needs. Also architected and drive development of multi-vendor solutions for custom silicon and lead teams to successful tape outs Defined, developed and deployed methodologies for custom silicon and significantly improved efficiency for Silicon Organization, Positive impact made on 900+ Engineers Silicon Department. Close collaboration with EDA and AI solution partners, leading TRMs (technical review meetings) and many successful initiative/evaluations for new technology adaptation for large scale SoCs and IPs. Successfully lead an effort of AI tools evaluation; implementation to integrate tools in to Front End flow, defined and deployed AI methodologies and helped team achieve goals faster with significant cost saving. Worked on large scale SoCs and cross functional teams, understanding compute needs and helping set the methodology to save significant on hardware compute and licensing. Hiring and building teams for front End DV and Methodology (India, Austin, Sweden), reach out for more details.

DAC2026, Session Chair for the Front End Track, Session Topic, "Concept to Confidence, The AI Evolution in Design Verification" https://63dac.conference-program.com/presenter/?uid=505843 DAC2023, Session Chair for the Front End Track, Session Topic: “The Next Frontiers in the Front End” https://60dac.conference-program.com/session/?sess=sess189 DAC2022, Session Chair for Front Design Track. Session topic : "New Developments in Security Verification and Controlling Unpredictable Behavior "More details @ https://59dac.conference-program.com/session/?sess=sess162

Active member and contributor to various electronic print media, like www.EDACafe.com https://www10.edacafe.com/blogs/asicwithankit/ EETimes India www.SemiWiki.com www.electronicsmaker.com www.testbench.in ASIC With Ankit @ www.asicwithankit.com Actively writing blog posts for Design Verification Community. Sharing my experience and also learning from industry experts. - 300K+ blog page hits and continuing. The best way to improve your knowledge is 'to Share'. The goal is to share design verification knowledge to a community and to learn from the experts. -ASIC With Ankit

Built and Lead XNE FE TFM task force and drove Front End Tools flows and methodology for complex SoCs and IPs for Xeon Server Networking for 5G products. Built team lead team in different geography (Austin, Santa Clara and Cota Rica) Close collaboration with EDA vendors, many successful initiative/evaluations for new technology adaptation for large scale SoCs and IPs, New Front End Tools Deployment for various groups at Intel to help teams achieve their project goals on time with quality and accuracy. Significantly improved build time 18x for large scale SoC by implementing elaboration technique and utilizing best TFM methods (Tools flows and Methodology) Successfully implemented and deployed customized save/restore for test benches to save up to 50% TAT time on large SoCs. Successfully integrated VCS DTL (Dynamic Test Loading) flow which helped SOC team achieve up to 100x test development and debug process. Deployed this flow to various IPs and SoCs. Lead multiple vendor tools & technologies evaluations at different SoCs and driving deployment of various technologies, like Cadence’s MSIE, Synopsys's VCS’s Partition Compile, Dynamic Test Loading (DTL), Turbo Compile (TC), Verdi VMS (Verification Management System), ICO (intelligent coverage optimization), VSO.ai, Jasper Connectivity, VCLint, CDC. RDC, also leading effort on new technologies under Limited Customer Availability (LCA). Established close collaborative effort with cross functional teams to drive many exciting and early adopter initiatives around tool flows and methodologies and drive team to successful production use and help team tapes out on time. Received multiple department level recognition for significant impact for multiple teams.

Advisory Board for the Digital Marketing Executive Education Program at Cal Poly Pomona Enterprises. Joining Cal Poly's mission to link industry with academia to ensure their work is relevant and beneficial. Advisory Board Member profile @ https://www.cppexec.education/ankit-gopani.html

Advisory Board for The University of California Irvine's Division of Continuing Education at San Diego focusing on Customer Experience Certificate Program! It is UCI's mission to link industry with academia to ensure their work is relevant and beneficial. Advisory Board Member profile @ https://cx.ce.uci.edu/ankit-gopani.html

Worked for Systems and Advanced Verification Group, lead Front End DV team for south California, worked closely with many companies and help solve their challenges in DV flow. Took ownership of large scale IP subsystem teams and migrated them from to Cadence flow (Xcelium, Jasper, vManager) successfully! Close collaboration with various IP teams in the field of Power Management, RF, Modem, Bluetooth, SoC, Audio, Video, Camera and CAD. Design Verification, Constraint random verification, UVM, System Verilog VIP (various VIP solutions) integration and support for complex SoC Environments, Simulation activities, RTL, Gate Level, functional and Code Coverage Closure for complex ASICs Functional Safety Flow and Industry-standard verification methodology bring up. Build customer relationships and Successfully worked, managed and drive key customer projects.

Responsible for Block verification(SV-UVM) for mobile platform audio codec chips. Worked on Coverage Driven Verification Framework for Regression to hit maximum Functional Coverage. Verification included developing SV-UVM based tests, testbench and coverage for: - Developing register models, RDB and developing register sequences, - Developing SWI register functional tests using a serial interfaces - Reference models(in C/Matlab) were integrated using monitors/scoreboards in testbench. - Verifying different power modes in the chip were functionally correct: wake up from sleep, memory contents - - Responsible for settting jasper formal verification flow for block-level test benches and run through the connectivity at SoC level. Closely working with designer and system team to understand the requirement to achieve the coverage-driven verification goals for closer.

A certified DO-254 Engineer with hands-on experience in executing avionics projects. Worked on various FPGA design and verification projects. - Closely worked with designers and team to achieve the verification goal and coverage closures. - Worked on various projects with different level of safety certification.

Worked as a Sr Design Verification Engineer and executed various customer projects for block level as well as SoC level verification with Verilog, System Verilog and UVM