Joshua Mora
About
Joshua Mora is from Austin, Texas, United States. Joshua is currently Chief Executive Officer at SYSTEM-STACK, located in Austin, Texas, United States. In Joshua's previous role as a Principal Engineer, architecting next gen large scale AI solutions at Intel Corporation, Joshua worked in Austin, Texas, United States until Nov 2024. Prior to joining Intel Corporation, Joshua was a Principal Architect at NVIDIA and held the position of Principal Architect at Santa Clara. Prior to that, Joshua was a Chief Architect of microprocessor and applications for HPC and Big Data at FutureWei Technologies, based in Santa Clara, California from Dec 2017 to Sep 2018. Joshua started working as Principal Member Of Technical Staff at AMD in Austin, Texas Area in Apr 2016. From Mar 2013 to Apr 2016, Joshua was R&D SW+HW for HPC, World Wide Provider at HPCguru,LLC, based in World Wide. Prior to that, Joshua was a Director of Research and Development of Cloud Technology at Artisan Infrastructure, based in Austin, Texas Area from Jun 2015 to Nov 2015. Joshua started working as Principal Member of Technical Staff at Advanced Micro Devices in Sunnyvale in Apr 2013.
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Joshua Mora's current jobs
Bringing next level of resiliency and performance to very large scale HPC and AI infrastructures. Boosting datacenter revenues.
Joshua Mora's past jobs
Research, development and optimization of next generation of supercomputing based solutions (HW+SW) (large scale computation, strong scaling) applied to AI markets.
Research, development and optimization of next generation of supercomputing based solutions (HW+SW) (large scale computation, strong scaling) applied to AI markets.
Architecting Huawei's next generation solutions for HPC and Big Data markets. See the link below for a presentation/summary of the work I have been driving during the 10 months at Huawei.
Ramp up leadership support for technical, business, marketing on the design of EPYC based (compute + storage) server systems, top US+China accounts for Cloud and HPC markets world wide.
World Wide professional services provided: + HPC hands on work Short term (few days) hands on work, to root cause and fix SW or and HW problems in your current HPC solutions. Benchmarking and performance analysis. Mid term SW or/and HW research and development (upto 1 year) of HPC solutions. + HPC brainstorming From concept to implementation: Algorithms, Software, Hardware, Optimization, Efficiency, Productivity. + HPC strategy review HPC technology trends and analysis that align in time with your needs. Forward thinking to max out your Return Of Investment.
Wholesale Only Infrastructure For Cloud Solution Providers Enterprise grade, on-demand, platform supported by VMware, NetApp, HP, Arista, Brocade, and Cisco. R&D on Object Based Storage solutions
Responsible for end to end performance characterization, validation and tuning of Seamicro systems (CPU, memory, fabric:network and storage) for HPC and Big Data. Tuning of HPC applications (bioinformatics, oil and gas and molecular dynamics) leveraging 3D mesh network topology awareness and communication overlap. Development, Terasort tuning (YARN tuning, fabric custom routing) and validation of Hadoop 2.0 (YARN) (Cloudera, Hortonworks, MAPR) reference architecture on Seamicro with multi Petabyte storage infrastructure. Machine learning distributed algorithm development and performance assessment (MLP, Kmeans ++ parallel) Development of fault tolerance + network topology aware communication software framework with ZMQ.
World Wide HPC engineering/business support. Performance assesment/tuning of large scale scientific applications on next AMD's generation of multicore processors. Management of HPC infrastructure at AMD performance lab. F1 processor design wins , 2012 and 2010.
Performance assesment and tuning of large scale scientific applications on infiniband based clusters with AMD multi socket/core processors.