Prashant Joshi

• Leading an Engineering team to develop next generation vehicle architecture for high speed sensors and low speed communication. • Interfacing with in-house systems teams, FW/SW teams to understand the silicon requirements and define the Silicon architecture and Cost Target for the ASICs. • Work with GSM and Biz team for negotiations with vendors and foundries. • Work with ASIC vendors to define micro-architecture, define EDA tool methodologies and set timelines/milestones. • Interfacing with 3rd party IP providers to customize IP functionality and features to meet the spec. • Defined full chip power management, clock and reset strategies during silicon development. • Provide direction to ASIC vendor on implementation, PPA tradeoffs, timing closure, power closure. • Enable FPGA validation by design partitioning and use it for Firmware development. • Hold Tapeout reviews with 3rd party IP providers for integration and ASIC vendors for sign off on Tape-Out of Silicon. • Work with Foundries on leading edge Nodes to enable process tweaks to meet power budget and resolve Yield issues. • Develop the strategy and oversee Validation for Silicon using prototype boards during DVT/PVT and through production • Work with in-house thermal team for simulations and package selection • Work with ASIC vendor, package design team and board design teams for optimal package design • Work with in-house experts to define parameters for silicon test • Help with ATE and prioritize test debug at the ATE house. • Provided review and debug support for 3rd party FPGA designs in the vehicle.

Joined Uniquify Inc through Uniquify’s acquisition of Comit Systems Inc. Leading a team of engineers on multiple projects that include logic design, verification, DFT flow setup and ASIC DFT architecture, implementation and interface with customer and in-house PD groups. Managed 12+ ASIC programs for logic design, verification, DFT and test engineering. As an Architect for DFT, Synthesis and STA methodologies I lead team of 10+ engineers and Interfaced with customer to understand ASIC implementation objectives such as define full chip DFT architecture, DFT flow development, help test engineers develop test program and support production. This design instantiated over 70Mb of memory bits spanned over 3200+ memories and over 5M flops, included multiple instances of third party 10G SERDES and few other analog, mixed signal macros. I was responsible for block level and full chip Synthesis, DFT, ATPG, STA flow, Coordinated with PD team for timing closure in all test modes. I also coordinated with the test engineers for Silicon bring-up on the ATE and was responsible for supporting team of engineers for ATE failure analysis . I also lead team of 6 engineers and worked on a SoC implementation and FPGA prototype. My responsibilities were to collaborated with customer to understand and implement the chip functional requirements. SoC included various 3rd party IPs such as 2 Tensilica processors, Arteris NOC, GIGE MAC, multiple instances of UART, GPIO, I2C, MMC/SDIO cards interface, DDR3 Controller + PHY, DMA controllers. Design was prototyped using Xilinx FPGA. I Integrated 3rd party IPs in RTL and was FPGA bring up and debug. I also worked on creating all mode SDCs, synthesis, and timing analysis and coordinated with physical design group for successful hierarchical implementation and timing closure for TSMC 65G process node.

As a VP Engineering: Actively supported sales and marketing teams to earn business Lead engineering teams to successfully complete ASIC/SoC/FPGA programs Interacted with customers and 3rd party vendors for ASIC tool flows, IP selection Interfaced with Comit India office team on execution of projects

As a lead for ASIC implementation and FPGA prototype. Worked on six generations of 2wire DSL CPE modems implementing DSL, ADSL, ADSL+, Bonded ADSL and VDSL protocols. Responsibilities included Multi TX-RX channel scatter-father DMA design and implementation to interface with multiple GIGE, PCIE, USB2, Crypto processor and various DSL blocks. I was personally responsible for integrating 2 Tensilica processors with custom TIE instruction blocks and cache coherency modules. Responsible for architecting, designing and implementing the Crypto processor catered to DSL applications that included hashing engines like SHA1, SHA2, MD5 and encryption engines like RC4, AES, DES/3DES supporting ECB, CBC, OFB, CFB modes of operation. The Crypto processor also supported AES based secured booting from on board flash. For bonded ADSL2+ design, worked on Packet splitting and aggregation engine for 2 DSL lines, line bandwidth control mechanism, in-band control packet management, line training with Conexant, copper gate AFE interface. Also responsible for full chip Synthesis, STA, DFT insertion and worked with 3rd party vendor for full chip timing closure in all modes. Supported ATPG pattern generation and test bring-up on the ATE, debugging the test failures and analyzing the failing vectors. Developed a custom cell derate timing analysis methodology to analyze failures on SF, FS corner parts to improve production yield significantly.

As a project manager, i was responsible for internal project execution and customer interface on technical matters like micro architecture development. Lead team of talented engineers to execute multiple tasks in the area of Networking and wireless home entertainment systems. Worked on a design as a team lead for a OC48 network processor to protocol independent switch Fabric Bridge implementation. Implemented Agere Orca series FPSC’s based protocol conversion bridge to support OC48 network processor packet management with a protocol independent switch fabric. I was involved as an architect for the design, design partitioning across multiple FPSC's and also handled design of a Full duplex traffic control and packet processing engines for 2.5Gbps SERDES interfaces, 1:1 redundancy for backplane, Utopia L3 compliant network processor interface, Diagnostics features; test cell monitoring, data integrity check, serial/parallel loop-back. As a team lead for ASIC and FPGA implementation worked on a wireless home entertainment system that targeted HiperLAN protocol. Designed a ARM7 based Channel Access Controller (equivalent of a MAC in Ethernet) for the RF interface module. Developed and integrated infrastructure IPs around ARM7 processor for full functionality.

Joined Wipro technologies as a senior engineer to work on Analog Devices 2106x DSP processor family based products. Grew from senior engineer to project lead at Wipro and worked on two major designs in the digital audio and video domain. An FPGA based implementation for an audio synthesis system working with Analog Devices AD21065 DSP processors. Personally worked on an FPGA and system board that included PCI interface, SDRAM controller, MIDI, FLASH interfaces. An FPGA and ASIC implementation of Extended video co-processor. Personally worked on RTL design and FPGA bring up of CCIR656 compliant display controller, Analog Devices DSP (ADSP2106x) processor bus functional models in verilog